View UPC1862_131198.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
PC1862
BURST LOCK CLOCK GENERATOR
The PC1862 is an LSI incorporating a PLL circuit to generate nfSC clocks (fSC: color subcarrier frequency), ideal for the processing of digital video signals as in extended definition television (EDTV) systems.
FEATURES
* VCO is incorporated. * Horizontal and vertical sync separation circuits are incorporated (with output pins). * Horizontal and vertical sync output pulses (TTL level) * ACC amplifier and killer detector circuits are incorporated. * 1/4 and 1/8 (1/2 x 1/4) frequency dividers are incorporated. * fSC phase control circuits is incorporated. * Applicable to both NTSC and PAL systems. * Possible to input burst gate pulse from external
ORDERING INFORMATION
Part number Package 36-pin plastic shrink SOP (300 mil)
PC1862GS
The information in this document is subject to change without notice. Document No. S11431EJ3V0DS00 (3rd edition) Date Published December 1997 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1991, 1996
PC1862
BLOCK DIAGRAM
SSI CSO 36 35 34 VSSI HDF 33 32 HDO HKO 31 SGND HSOF2 AFCF BGPE CPO VSO HSOF1 HSOF3 SVCC NHSO FIO N/P 30 29 28 27 26 25 24 23 22 21 20 19
H sync SEP
V sync SEP
H DET
32fH VCO
AFC
H count down
LPF
ACC DET
V count down
f 2
f 4
Phase shift
ACC AMP
Color Killer DET
APC
nfSC VCO
1 SCO
2 CVCC1
3 TINT
4 CIN
5 ACCF
6 CKO
7 CKF
8
9
10
11
12
13
14
15
16
17
18
APCF SCOF1 SCOF3 CVCC3 DIVS COUT CGND SCOF2 CVCC2 VCOO ESCI
Remark AFC : Automatic Frequency Control ACC : Automatic Color saturation level Control APC : Automatic Phase Control Selecting divide ratio by DIVS pin
DIVS H Open L 1/8 EXT IN with pin 18 1/4 Divide ratio H L
Selecting TV transmission by N/P pin
N/P pin PAL NTSC TV transmission
In PAL, only correspond 4fSC (DIVS = L).
2
PC1862
System Block Diagram Application to Process of Digital Video Signal
Gate array, etc Analog video input A/D converter PC659A Processing of digital video D/A converter PC665 (1ch.) PC664 (2ch.) PC662 (3ch.) Analog video output
Clock generator PC1862
3
PC1862
PIN CONFIGURATION (Top View)
36-pin plastic shrink SOP (300 mil)
SCO CVCC1 TINT CIN ACCF CKO CKF COUT APCF CGND SCOF1 SCOF2 SCOF3 CVCC2 CVCC3 VCOO DIVS ESCI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 SSI CSO VSSI HDF HDO HKO SGND HSOF1 HSOF2 HSOF3 AFCF SVCC BGPE NHSO CPO FIO VSO N/P
4
PC1862
ACCF AFCF APCF BGPE CGND CIN CKF CKO COUT CPO CSO CVCC1-CVCC3 DIVS ESCI FIO HDF HDO HKO HSOF1-HSOF3 NHSO N/P SCO SCOF1-SCOF3 SGND SSI SVCC TINT VCOO VSO VSSI : Chroma ACC Filter : Horizontal Sync AFC Filter : Chroma APC Filter : Burst Gate Pulse from External : Chroma GND : Chroma Input : Color Killer Filter : Color Killer Output : Chroma Output : Clamp Pulse Output : Composite Sync Output : Chroma VCC : Divider Setting Input : External Subcarrier Input : Field ID Output : Horizontal Sync Detect Filter : Horizontal Sync Detect Output : Horizontal Sync Killer Output : 32fH VCO Filter : Negative Horizontal Sync Output : NTSC/PAL Mode Select : Subcarrier Output : fSC VCO Filter : Sync GND : Horizontal Sync Separation Input : Sync VCC : Tint Control : VCO Output : Vertical Sync Output : Vertical Sync Separation Input
5
PC1862
PIN FUNCTIONS
(1/12)
Pin No. 1 Symbol SCO Pin Name Sub Carrier Output Equivalent Circuit
CVCC3 (pin 15)
Function Burst locked sub carrier output
5 k
1 400 A
DC voltage of a standard 2 CVCC1 Chroma VCC1
2.9 V Power supply for chroma signal processing circuit (pin 1 to pin 18) This power supply must be isolated from the power supply for sync processing circuit use.
3
TINT
Tint Control
CVCC3 (pin 15) 3.3 V 5 k 100 A 15 k
Tint control input (DC voltage) This pin adjusts the tint of sub carrier output (SCO pin).
3
Internal bias voltage of a standard
2.5 V
6
PC1862
(2/12)
Pin No. 4 Symbol CIN Pin Name Chroma Signal Input
4.0 V 10 k 5 k
Equivalent Circuit
CVCC1 (pin 2)
Function Chroma signal input
100 A 200 A 4
Internal bias voltage of a standard 5 ACCF Chroma ACC Filter
3.2 V Pin for connecting filter of ACC (Automatic Color Control) detector
CVCC3 (pin 15)
2 k
200
2 k 5
DC voltage of a standardNote 6 CKO Color Killer Output
1.0 V Color Killer Detection output When Killer (without burst) signal: Low level output When color signal: High level output
CVCC3 (pin 15)
1 k 6
Note
Chroma burst amplitude from pin 4: 150 mVp-p
7
PC1862
(3/12)
Pin No. 7 Symbol CKF Pin Name Chroma Killer Filter
1 k
Equivalent Circuit
CVCC3 (pin 15) 3.6 V 2 k 500
Function Pin for connecting filter of Color killter detector
14 k
1 k
7
DC voltage of a standardNote 8 COUT Chroma Signal Output
2.2 V Automatic color controlled chroma output
CVCC3 (pin 15)
5 k
For APC circuit
8 400 A
DC voltage of a standard
2.4 V
Note
Chroma burst amplitude from pin 4: 150 mVp-p
8
PC1862
(4/12)
Pin No. 9 Symbol APCF Pin Name APC Filter 1 k 12 k Equivalent Circuit Function Pin for connecting filter of APC (Automatic Phase Control) detector
5 k
60 k 65 k 1.8 V 4.5 k
1 k
9 DC voltage of a standardNote 10 CGND Chroma GND 2.7 V Ground for chroma signal processing circuit (pin 1 to pin 18)
11
SCOF1
nfSC VCO Filter (1)
CVCC2 (pin 14)
Pin for connecting filter of nfSC VCO
500 11
200 A
Bias voltage of a standard
3.0 V
Note
Chroma burst amplitude from pin 4: 150 mVp-p
9
PC1862
(5/12)
Pin No. 12 Symbol SCOF2 Pin Name nfSC VCO Filter (2)
3.8 V 20 k 1 k 1 k
Equivalent Circuit
Function Pin for connecting filter of nfSC CVCC2 (pin 14) VCO
200 A
200 A
12
Internal bias voltage of a standard 13 SCOF3 nfSC VCO Filter (3)
3.0 V Pin for connecting filter of nfSC VCO
CVCC2 (pin 14)
13 200 A 1 mA
DC voltage of a standard 14 CVCC2 Chroma VCC 2
2.9 V Power supply for chroma signal processing circuit (pin 1 to pin 18) This power supply must be isolated from the power supply for sync processing circuit use.
15
CVCC3
Chroma VCC 3
Power supply for chroma signal processing circuit (pin 1 to pin 18) This power supply must be isolated from the power supply for sync processing circuit use.
10
PC1862
(6/12)
Pin No. 16 Symbol VCOO Pin Name VCO Output Equivalent Circuit Function Burst locked VCO output
CVCC2 (pin 14)
5 k
16 400 A
DC voltage of a standard 17 DIVS Dividing ratio selection
25 k 100 A 100 A
2.8 V Divider ratio selection input CVCC3 (pin 15) When 1/4: Low level input When 1/8: High level input When external dividing: Middle level input
10 k
25 k 16 k 16 k 16 k 16 k
17
18
ESCI
External subcarrier Input (External Divide)
100 A 25 k
CVCC3 (pin 15)
External subcarrier input. When no use (pin 17 is not middle level): Low level input
2.5 V
5 k 18 22 k
11
PC1862
(7/12)
Pin No. 19 Symbol N/P Pin Name NTSC/PAL selection
100 A
Equivalent Circuit
CVCC3 (pin 15)
Function NTSC/PAL system selection input When NTSC system: Low level input When PAL system: High level input
5 k 19
2.0 V
16 k
20
VSO
Vertical Sync Output
SVCC (pin 25)
Negative polarity vertical sync output
1 k
40 k 20
21
FIO
Field ID Output
SVCC (pin 25)
1 k
40 k 21
Odd/Even field ID output When Odd ID: Low level output When Even ID: High level output When a input is non-standard signal, this pin outputs an indefiniteness.
22
CPO
Clamp Pulse Output
SVCC (pin 25)
Pedestal Clamp pulse (burst gate pulse) output
1 k
40 k 22
12
PC1862
(8/12)
Pin No. 23 Symbol NHSO Pin Name Negative Horizontal Sync Output Equivalent Circuit Function Negative polarity horizontal sync output
SVCC (pin 25)
1 k
40 k 23
24
BGPE
Burst Gate Pulse from External 2.5 k 5 k
SVCC (pin 25) 24
Burst gate pulse input In inside burst gate pulse generation mode: Low level fix In external burst gate pulse input mode: When Non-burst period: Middle level input When burst period: High level input Power supply for sync signal processing circuit (pin 19 to pin 36) This power supply must be isolated from the power supply for chroma processing circuit use.
8 k
5 k
7 k BGP
25
SVCC
Sync VCC
13
PC1862
(9/12)
Pin No. 26 Symbol AFCF Pin Name AFC Filter 200 3.2 V Equivalent Circuit SVCC (pin 25) Function Pin for connecting filter of horizontal AFC (Automatic Frequency Control) detector
300
3 k 30 k
100 A 1 k
26
DC voltage of a standardNote 27 HSOF3 32fH VCO Filter (3) SVCC (pin 25)
3.2 V Pin for connecting filter of 32fH VCO
27 1 mA
DC voltage of a standard 28 HSOF2 32fH VCO Filter (2) SVCC (pin 25) 4.6 V 3.3 k
2.4V Pin for connecting filter of 32fH VCO
100 A
28
Internal bias voltage of a standard
3.8 V
Note
When only 0.3 Vp-p sync signal is input to pin 36
14
PC1862
(10/12)
Pin No. 29 Symbol HSOF1 Pin Name 32fH VCO Filter (1) Equivalent Circuit Function Pin for connecting filter of 32fH VCO
29
Bias voltage of a standard 30 SGND Sync GND
3.8 V Ground for sync processing circuit (pin 19 to pin 36)
31
HKO
Horizontal Killer Output
31 24 k
Horizontal killer output (Open Corrector) When No sync: High impedance output When sync: Low level output
32
HDO
Horizontal Sync Detection Output
SVCC (pin 25)
Horizontal sync detection signal output When No sync: High level output When sync: Low level output
1 k 32
15
PC1862
(11/12)
Pin No. 33 Symbol HDF Pin Name Horizontal Sync Detection Filter Equivalent Circuit
SVCC (pin 25)
Function Pin for connecting filter of Horizontal sync detector
1 k
10 k
H gate pulse
33
Bias voltage of a standardNote 34 VSSI Vertical Sync Separator Input
16 k 20 k 100 1 k
4.1 V
Vertical sync separation input pin SVCC (pin 25) 5 k
30 k
34
35
CSO
Composite Sync Separator Output
SVCC (pin 25)
Negative polarity composite sync output
1 k 35
Note
When only 0.3 Vp-p sync signal is input to pin 36
16
PC1862
(12/12)
Pin No. 36 Symbol SSI Pin Name Horizontal Sync Separator Input
16 k 20 k 100 1 k 30 k
Equivalent Circuit
SVCC (pin 25) 5 k
Function Horizontal sync separation input pin
36
17
PC1862
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C, unless otherwise specified)
Parameter Supply voltage Input signal voltage (Chroma signal) Input signal voltage (H sync separation) Input signal voltage (V sync separation) Input signal voltage (EXT) Tint control signal voltage Output current Permissible package power dissipation (when mounted on PCB) Operating ambient temperature Storage temperature Symbol VCC ei4 ei36 ei34 ei18 ec3 IO PD Ratings 7 3 3 3 VCC VCC -7 570 (TA = 75C) Unit V Vp-p Vp-p Vp-p Vp-p V mA mW C C
TA Tstg
-10 to +75 -40 to +125
Caution Expose to Absolute Maximum Rating for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. RECOMMENDED OPERATING CONDITIONS
Parameter Supply voltage Input signal voltage (Chroma signal) Input signal voltage (H sync separation) Input signal voltage (V sync separation) Input signal voltage (EXT IN HIGH voltage) Input signal voltage (EXT IN LOW voltage) Divider selector voltage 1 (1/8) Divider selector voltage 2 (1/4) Tint control voltage NTSC/PAL select voltage (PAL) NTSC/PAL select voltage (NTSC) Symbol VCC ei4 ei36 ei34 eiH18 eiL18 V17 (8) V17 (4) V3 V19P V19N 4.5 0.5 2.5 4.8 0.2 2.0 0.8 MIN. 4.5 TYP. 5.0 150 1.0 1.0 MAX. 5.5 Unit V mVp-p Vp-p Vp-p V V V V V V V
18
PC1862
ELECTRICAL CHARACTERISTICS (at TA = 253 C, RH 70 %, VCC = 5 V, unless otherwise specified)
Chroma section
Parameter Supply current of chroma section ACC amplitude characteristic 1 Symbol ICC (C) Condition VCC (C) = 5 V No current on pin 2, 14 and 15 Fluctuation of chroma output level at +6 dB change of chroma input burst signal (0 dB = 150 mVp-p) Fluctuation of chroma output level at -20 dB change of chroma input burst signal (0 dB = 150 mVp-p) Input level at killer ON with chroma input burst sig. (0 dB = 150 mVp-p) being attenuated Residual level of chroma output in Killer ON state when chroma input burst signal of 150 mVp-p is input Chroma output level when chroma input burst signal of 150 mVp-p is input High level of color killer output at color killer OFF IOH = -400 A High level of color killer output at color killer OFF IOH = -20 A Low level of color killer output at color killer ON IOL = +2 mA Frequency pulled by APC with chroma input burst frequency changed (fSC conversion) Rate of variation of frequency when APC filter pin is changed from -0.025 V to +0.025 V (fSC conversion) Amount of phase shift when voltage of phase control pin is set at 2.5 V + 1 V VCO output level when chroma input burst signal of 150 mVp-p is input fSCO output level when chroma input burst signal of 150 mVp-p is input 1/4 freq. division if VDIVS < VDIVSL EXT IN with VDIVS : OPEN VDIVSH NTSC/PAL select voltage VN/PT 1/8 freq. division if VDIVSH < VDIVS fV = 60 Hz if VN/P < VN/PT fV = 50 Hz if VN/PT < VN/P 4.5 1.7 2.0 2.3 V V MIN. 17 TYP. 21 MAX. 25 Unit mA
ACC1
-2.0
0
+2.0
dB
ACC amplitude characteristic 2
ACC2
-5.0
-1.0
+1.0
dB
Color killer set point
eKS
-45
-39
-33
dB
Color residual of color killer
eKR
-
-
15
mVp-p
Chroma output level
ECOUT
1.1
1.3
1.5
Vp-p
Color killer output High level (1)
ECKOH (1)
2.7
3.5
-
V
Color killer output High level (2)
ECKOH (2)
3.5
4.0
-
V
Color killer output Low level APC lock-in range
ECKOL
400 8.0
0.2 600 10.0
0.4
V
fP
-
Hz
VCO control sensitivity
P
12.0
Hz/mV
Phase variable range
CONT
eVCOO
40 1.0
55 1.3
-
deg
VCO output level
1.6
Vp-p
fSC output level
eSCO
210
300
390
mVp-p
Divider select voltage
VDIVSL
-
-
0.5
V
19
PC1862
Sync section
Parameter Supply current of Sync section DC level of H sync separation input DC level of V sync separation input Sync separation output High level (1) Symbol ICC (1) Condition VCC (1) = 5 V No current on pin 25 Voltage of pin 36 when connected to GND via 10 k resistor Voltage of pin 34 when connected to GND via 10 k resistor High level of sync separation output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -400 A High level of sync separation output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -20 A Low level of sync separation output when only 0.3 Vp-p sync signal is input to pin 36 IOL = +2 mA High level of synchronized HD output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -400 A High level of synchronized HD output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -20 A High level of synchronized HD output when only 0.3 Vp-p sync signal is input to pin 36 IOL = +2 mA High level of synchronized VD output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -400 A High level of synchronized VD output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -20A High level of synchronized VD output when only 0.3 Vp-p sync signal is input to pin 36 IOL = +2 mA High level of synchronized Clamp output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -400 A High level of synchronized Clamp output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -20 A High level of synchronized Clamp output when only 0.3 Vp-p sync signal is input to pin 36 IOL= +2 mA MIN. 12 TYP. 15 MAX. 18 Unit mA
VSSI
1.9
2.2
2.5
V
VVSSI
1.9
2.2
2.5
V
ECSOH1
2.7
3.8
-
V
Sync separation output High level (2)
ECSOH2
3.5
4.3
-
V
Sync separation output Low level
ECSOL
-
0.1
0.4
V
HD output High level (1)
ENHSOH1
2.7
3.8
-
V
HD output High level (2)
ENHSOH2
3.5
4.3
-
V
HD output Low level
ENHSOL
-
0.1
0.4
V
VD output High level (1)
EVSOH1
2.7
3.8
-
V
VD output High level (2)
EVSOH2
3.5
4.3
-
V
VD output Low level
EVSOL
-
0.1
0.4
V
Clamp output High level (1)
ECPOH1
2.7
3.8
-
V
Clamp output High level (2)
ECPOH2
3.5
4.3
-
V
Clamp output Low level
ECPOL
-
0.1
0.4
V
20
PC1862
Parameter Field ident. output High level (1) Symbol EFIOH1 Condition High level of synchronized Field ident. output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -400 A High level of synchronized Field ident. output when only 0.3 Vp-p sync signal is input to pin 36 IOH = -20 A High level of synchronized Field ident. output when only 0.3 Vp-p sync signal is input to pin 36 IOL = +2 mA High level of asynchronized H detect output without H sync input IOH = -400 A High level of asynchronized H detect output without H sync input IOH = -20 A High level of synchronized H detect output when only 0.3 Vp-p sync signal is input to pin 36 IOL= +2 mA Frequency range that can be pulled when only 0.3 Vp-p sync signal is input to pin 36 and H sync frequency is varied (fSC conversion) Rate of variation of frequency when APC filter pin is changed form 3.0 V to 3.4 V without H sync input (fSC conversion) Frequency difference of HD output from fH when H sync input is not applied Pulse width of synchronized HD output when only 0.3 Vp-p sync signal is input to pin 36 Pulse width of synchronized VD output when only 0.3 Vp-p sync signal is input to pin 36 ODD EVEN MIN. 2.7 TYP. 3.8 MAX. Unit V
Field ident. output High level (2)
EFIOH2
3.5
4.3
-
V
Field idnet. output Low level
EFIOL
-
0.1
0.4
V
H detection output High level (1)
EFIOH1
2.7
3.8
-
V
H detection output High level (2)
EFIOH2
3.5
4.3
-
V
H detection output Low level
EFIOL
-
0.1
0.4
V
H sync lock-in range
fHP
400
500
-
Hz
Horizontal VCO control sensitivity
H
-1.6
-1.3
-0.9
Hz/mV
Horizontal VCO free-run frequency Pulse width of HD output
fHO
-100
-25
+50
Hz
PWNHSO
3.8
4.0
4.2
s
HNote HNote
Pulse width of VD output
PWVSO1 PWVSO2
3.4
6.0 5.5 3.6
3.8
Pulse width of Clamp output
PWCPO
Pulse width of synchronized Clamp output when only 0.3 Vp-p sync signal is input to pin 36 Output voltage at HD when VCC is gradually increased from 0 V without H sync input Low level of synchronized H killer output when only 0.3 Vp-p sync signal is input to pin 36 Change value of Chroma output Burst gate pulse input voltage when Clamp voltage begins Low level is gradually increased from 0 V without signal input
s
V
Oscillation start voltage of horizontal VCO H killer output Low level
VST
-
-
4.2
EHKOL
-
-
0.4
V
Burst gate input Threshold level 1
VBGPE1
1.6
1.9
2.0
V
Note
H: Horizontal scanning period
21
PC1862
Parameter Burst gate input Threshold level 2 Symbol VBGPE2 Condition Burst gate pulse input voltage when Clamp voltage begins High level is gradually increased from VBGPE1 without signal input Frequency ratio of HD output to VD output H sync input: No signal Pin 33 input: VCC V sync input: VCC Same as fV1 with the following exception V sync input: GND Same as fV1 with the following exception Pin 33 input: GND Same as fV1 with the following exception Pin 33 input: GND V sync input: GND MIN. 3.8 TYP. 4.0 MAX. 4.2 Unit V
Vertical free-running frequency 1
fV1 (50) fV1 (60)
-
fH/352 fH/288
-
Hz Hz
Vertical free-running frequency 2 Vertical free-running frequency 3 Vertical free-running frequency 4
fV2 (50) fV2 (60) fV3 (50) fV3 (60) fV4 (50) fV4 (60)
-
fH/288 fH/240 fH/368 fH/296 fH/272 fH/232
-
Hz Hz Hz Hz Hz Hz
22
PC1862
TIMING CHARTS (Horizontal Period)
1 s Burst Signal Comp Video Input
Comp Sync Output (CSO)
This delay is fixed by the application of pin 36. HD Output (NHSO) 4 s
4 s CLAMP Output (CPO) This rising edge is cut by Comp Sync Output.
23
24
TIMING CHARTS (Vertical Period)

Comp Video Input
HD Output (NHSO) CLAMP Output (CPO) VD Output (VSO) FIELD Output (FIO) 6 HNote 0.5 HNote

Comp Video Input
HD Output (NHSO) CLAMP Output (CPO) VD Output (VSO) FIELD Output (FIO) 5.5 HNote 0.5 HNote
PC1862
Note
H: Horizontal scanning period
PC1862
CAUTION AT DESIGNING
Resonators NEC evaluates PC1862 using resonators which are shown below in design and development process. If the different product is used as a resonator, electrical specification value described in this document is not assured. And when connecting resonator to external circuit, there is need to consider temperature specification, voltage fluctuation and product variation. In this case, normal operation is not assured in the application circuit including the different product. Use the resonators which are shown below when you design circuit. 32 fH VCO resonator X1 X1 (PAL) : in application example circuit : CSB500F2 (MURATA)
(NTSC) : CSB503F2 (MURATA) nfSC VCO resonator X2 X2 : HC-49/U (KINSEKI, PC1860 adoption)
Reference data of 4fSC, 8fSC VCO resonator (KINSEKI)
Item Name Frequency Overtone Order Operating Temperature Frequency Permitted Tolerance (255C) Frequency Temperature Specification (to 25C) Equivalent Serial Resistance Parallel Capacitance 3rd harmonic standard
NTSC for 4fSC
NTSC for 8fSC HC-49/U
PAL for 4fSC
14.31818 MHz Fundamental (AT cut)
28.63636 MHz Fundamental (BT cut) -10 to +70C
17.34475 MHz Fundamental (AT cut)
30 x 10-6 30 x 10-6
50 x 10-6 100 x 10-6 50 or less 7.0 pF or less
30 x 10-6 30 x 10-6
3rd harmonic frequency is over 3fO (42.95454 MHz) + 7.5 kHz
-
3rd harmonic frequency is over 3fO (53.203425 MHz) + 7.5 kHz
25
PC1862
Recommended pattern The PC1862 generates system clock for synchronous signal processing and clock generate processing. If the supply voltage, line placement and routing are not set appropriately that the PC1862 cannot generate correct system clock. Though the recommended pattern is not shows in this document, note points shown below at designing. 1. 2. 3. For synchronous section and chroma section, each power supply must be isolated. Lines to pin 9 to pin 13 should be as thick and short as possible. Connect resonator as near IC as possible. Don't put GND line between resonator pins for parasitism capacitance.
26
APPLICATION CIRCUIT
5V
1 k
X1:CSB503F2(Murata)
Comp sync OUT + 1000 pF 100 k 4.7 F + 220 100 k 0.01 F
Burst gate input `H': In the period of burst `M': Out the period of burst `L': Internal HD Clamp output Field ID output VD NTSC/PAL
Comp video IN
39 k 10 F + 75 11 k
2SA1175 4.7 F or equivalent 100 k 220
H DET OUT
1.5 k
220 pF 2.2 k
1500 pF 270 X1
8.2 2.7 k k 4.7 F
0.015 F 5V +
36
35
34
33
32
31
30
SGND
29
28
27
26
25
SVCC
24
23
22
21
20
19
H sync SEP
V sync SEP
H DET
32fH VCO
AFC
H count down
LPF BPF
47 pF 68 pF 15 H 680 0.01 F 10 k 5V fSC OUT 2SC2785 or equivalent 0.01 F 680 5V
ACC DET
V count down
f 2
f 4
Phase shift
ACC AMP
Color killer DET
APC
nfSC VCO
CGND 1 2 3 4
0.1 F
5
6
7
8
9
10
11
510
12
68 pF X2 C2 C1
13
100
14
5V
15
16
17
18
+
Tint cont.
0.47 F 0.01 F
+ 1 M 5V 0.1 F
2.2 k
Chroma IN
4.7 k
Color killer OUT
10 k
+ 4.7 Chroma F
0.022 F
2.2 k
External subcarrier input
VCO OUT `H' ...1/8 `M' ...EXT `L' ...1/4
Divider ratio select input
PC1862
OUT
X2:HC-49/U(KINSEKI)
X2 8 fSC 4 fSC NTSC C1 18 pF No connect (N/P =`L') C2 22 pF 10 pF PAL C1 12 pF - (N/P =`H') C2 18 pF - Cannot correspond 8fSC of PAL.
27
PC1862
Care Point for Planning of Application Circuit 1. Processing of VCC pin Please isolate Chroma. VCC from Sync. VCC as follows. If you have external processing block of digital signal, don't directly supply of the block's VDD.
5V
0.01 F 47 F
VDD Processing IC of digital signal, etc GND CVCC1 2
30 25 SVCC SGND Sync (Pin 19 to pin 36) PC1862 Chroma (Pin 1 to pin 18) CGND 10 CVCC2 14 CVCC3 15
0.01 F
47 F
0.01 F
2.
Application of no using Chroma pin If you don't use Chroma pin but use Sync pin on PC1862, you process pin 1 to pin 18 as follows.
PC1862
5V SCO CVCC1 TINT 1 2 3 CIN ACCF CKO CKF COUT APCF CGND SCOF1 SCOF2 SCOF3 CVCC2 CVCC3 VCOO DIVS ESCI 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
0.01 F
47 F 0.01 F
3.
Application of no using Sync pin If you don't use Sync pin but use Chroma pin on PC1862, you process pin 19 to pin 36 as follows. In this case, you need to input a pin 24 with burst gate pulse from external. In this application, you can't use output of pin 20 to pin 23.
Video signal input Comp Sync Output 5V Open 36 SSI 35 34 33 32 31 30 2.2 k 29 28 27 26 3.3 k 25 24 23
5V 0V 3.3 k
Burst Gate Input Open (Don't use) 22 21 FIO 20 VSO 19 N/P
CSO VSSI HDF HDO HKO SGND HSOF1 HSOF2 HSOF3 AFCF SVCC BGPE NHSO CPO
PC1862
28
PC1862
PACKAGE DRAWING
36 PIN PLASTIC SHRINK SOP (300 mil)
36
19
detail of lead end
1 A
18
55
H I
G
J
F
K
E
C D MM
N
B
L
P36GM-80-300B-3 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 15.54 MAX. 0.97 MAX. 0.8 (T.P.)
+0.10 0.35 -0.05
INCHES 0.612 MAX. 0.039 MAX. 0.031 (T.P.) 0.014+0.004 -0.003 0.005 0.003 0.071 MAX. 0.061 0.303 0.012 0.220 0.043 0.008+0.004 -0.002 0.024 -0.009 0.004 0.004
+0.008
0.125 0.075 1.8 MAX. 1.55 7.7 0.3 5.6 1.1 0.20 +0.10 -0.05 0.6 0.2 0.10 0.10
29
PC1862
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Surface Mount Device
PC1862GS: 36-pin plastic shrink SOP (300 mil)
Process Infrared ray reflow Conditions Peak temperature: 235 C or below (Package surface temperature), Reflow time: 30 seconds or less (at 210 C or higher), Maximum number of reflow processes: 2 times. Peak temperature: 215 C or below (Package surface temperature), Reflow time: 40 seconds or less (at 200 C or higher), Maximum number of reflow processes: 2 times. Wave Soldering Solder temperature: 260 C or below, Flow time: 10 seconds or less, Maximum number of flow process: 1 time, Pre-heating temperature: 120 C or below (Package surface temperature). Pin temperature: 300 C or below, Heat time: 3 seconds or less (Per each side of the device). WS60-00-1 Symbol IR35-00-2
VPS
VP15-00-2
Partial heating method
-
Caution Apply only one kind of soldering condition to a device, except for "Partial heating method", or the device will be damaged by heat stress.
30
PC1862
[MEMO]
31
PC1862
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

▲Up To Search▲

Price & Availability of UPC1862

	To Download UPC1862 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .